Discussion about this post

User's avatar
Steven J. Newbury's avatar

For anybody interested, the code is all going up on GitHub. I'll post a link when it's live.

Jon Rowlands's avatar

I used to write for digital signal processors and custom video chips and accelerators. What you're proposing sounds a lot like that, where the algorithm was strategically mapped to the hardware for a single purpose and maximum efficiency. It was great fun to do, and matched a time when hardware was always on the critical path of feasibility. We sometimes tried kernels that essentially virtualized the accelerators, and always returned to managing that by hand as you're proposing. The challenge was twofold. One was that the optimal hardware became very sensitive to small changes in the system requirements. It wasn't possible to "just" add memory or increase clock for the next chip, because tying the hardware and software architectures often moved the performance bottlenecks a lot when the requirements changed a little, and led to significant hardware revision. The second was that it became increasingly hard to find people that liked working in this mode, while at the same time the hardware improvements outstripped the software needs. This eventually pushed everything back towards fewer accelerators and more powerful CPU. You may be right that AI has flipped this back in the other direction. Firstly because problems are now again very much performance limited, and more interestingly because AI itself might solve the availability of programmers. AI is great at solving the kinds of tricky puzzles encountered while aligning software and hardware architectures, *if* the problems are well enough modeled. So I suspect that this will put you into a new situation where you're not just codesigning hardware and software, but also compiler and (this is the new part) programmer. What a time to be alive.

2 more comments...

No posts

Ready for more?